1. Field of the Invention
The present invention relates to a mask ROM (read only memory) and, in particular, to a memory cell structure for a large-capacity mask ROM for storing a plural-bit data (2.sup.n data).
2. Description of the Related Art
Generally a large-capacity mask ROM stores, in its memory cells, binary data "1" and "0" such as the presence or absence of transistors, of an impurity implanted into channel regions and of contacts.
FIGS. 1 and 2, each, show a memory cell array of a conventional mask ROM and FIGS. 1 and 2 show a NOR type and NAND type structure, respectively. These arrangements allow "1" and "0" to be programmed by the presence or absence of an implanted impurity for the formation of channel regions.
In FIGS. 1 and 2, gate electrodes 52 are formed over active regions 51 overlying a semiconductor substrate and a gate insulating film, not shown, is formed between the gate electrode 52 and the active region 51. Conductive layers 54 are formed over an insulating interlayer, not shown, which covers the gate electrode 52 and active region 51. The end portion of the active region 51 makes contact with the conductive layer 54 via a corresponding contact hole 53.
In FIGS. 1 and 2, a system is adopted which stores one bit in each MOS transistor by implanting an impurity ion opposite in conductivity type to that of the active region 51 and controlling a threshold level involved.
In the arrangement shown above, a cell area for storing one bit depends upon the technique for the manufacture of transistors. Therefore, a large-capacity mask ROM can be achieved by reducing the cell size as indicated by a broken line in FIGS. 1 and 2. If the downsizing of cells reaches a design limit, a problem is involved that an achievable mask ROM capacity will be limited. That is, it has been difficult, therefore, to implement a still larger-capacity mask ROM.